Examples

.PS
# basic/acdiode.cir drawn: a 1 mA bias (with a 1 mA AC part) into a
# diode shunted by 100k; .ac sees the diode's small-signal model at
# that bias, rd = n Vt / Id = 25.9 ohm plus RS, against CJ + Cd.
# Card order kept; deck node 1 Va.
spice = 1
Va: (1.3,1.6)

Ibias: isource((0.3,0), (0.3,1.6), dc 1m ac 1m)
D1: diode(Va, (1.3,0), dmod)
Rsh: resistor((2.3,1.6), (2.3,0), 100k)

line from Ibias.N to Rsh.P
line from Ibias.P to Rsh.N
dot at Va; dot at D1.N
ground((0.8,0))
.model dmod d(is=1e-14 rs=10 cjo=5p tt=10n vj=0.8 m=0.4)
.ac oct 8 1k 100meg
.PE

.PS
# basic/acrlc.cir drawn: a 2 V / 45 degree drive into a pair of 10u
# coils coupled by k = 0.3; the secondary rings a series 5 ohm /
# 253.3p branch (f0 = 3.16 MHz) and a VCVS (x2) buffers the secondary
# into RE. Card order kept; deck nodes 1 In, 2 Pri, 3 Sec, 4 Vc,
# 5 Vout.
spice = 1
In:   (0.3,2)
Pri:  (1.4,2)
Sec:  (2.4,2)
Vc:   (3.5,2)
Vout: (5.1,2)

Vin: acsource(In, (0.3,0), ac 2 45)
RS: resistor(In, Pri, 50)
L1: inductor(Pri, (1.4,0), 10u)
L2: inductor(Sec, (2.4,0), 10u)
K12: coupling(L1, L2, 0.3)
RL: resistor(Sec, Vc, 5)
C2: capacitor(Vc, (3.5,0), 253.3p)
E1: vcvs(Vout, (5.1,0), (4.6,1.2), (4.6,0.8), 2)
RE: resistor((6.3,2), (6.3,0), 1k)

line from Sec to (2.4,2.6) then to (4.3,2.6) then to (4.3,1.2) then to E1.Cp
line from E1.Cn to (4.3,0.8) then to (4.3,0)
line from E1.P to RE.P
line from Vin.N to RE.N
dot at Sec
dot at L1.N; dot at L2.N; dot at C2.N; dot at (4.3,0); dot at E1.N
ground((0.85,0))
.ac lin 50 1meg 5meg
.PE

.PS
# Series RLC band-pass, output across R1:
# H = R/(R + j w L + 1/(j w C)); f0 = 1/(2 pi sqrt(L1 C1)) = 15.9 kHz,
# |H(f0)| = 1, bandwidth R1/(2 pi L1) = 7.96 kHz (Q = 2).
spice = 1
Vin: (0,1.5); Vout: (3,1.5)
V1: vsource(Vin, (0,0), AC 1)
L1: inductor(Vin, (1.5,1.5), 1m)
C1: capacitor(L1.N, Vout, 100n)
R1: resistor(Vout, (3,0), 50)
line from V1.N to R1.N
ground((1.5,0))
dot at Vout
"out" above at Vout + (0,0.05)
.ac dec 20 1k 1meg
.PE

.PS
# Common-emitter amplifier: divider bias R1/R2, collector load R3,
# emitter degeneration R4 (gain ~ -R3/R4), input coupled through C1.
spice = 1
Q1: npn((3,1.5), QN, "T₁")
Vb:   (2,1.5)
Vcc:  (5,3.5)
Vin:  (1,1.5)
Vout: (3.16,2.4)

V2: acsource((0.3,1.5), (0.3,0), SIN(0 10m 1k), "G₁")
C1: capacitor(Vin, Vb, 10u)
R1: resistor((2,3.5), Vb, 47k)
R2: resistor(Vb, (2,0), 10k)
R3: resistor((3.16,3.5), Vout, 4.7k)
R4: resistor(Q1.E, (3.16,0), 1k)
V1: vsource(Vcc, (5,0), DC 12, "VCC")

line from V2.P to C1.P
line from C1.N to Q1.B
line from R3.N to Q1.C
line from R3.N to (4.1,2.4); circle rad 0.04 at (4.14,2.4)
"out" ljust at (4.2,2.4)
line from R1.P to V1.P
line from V2.N to V1.N
dot at R1.N; dot at R3.P; dot at R2.N; dot at R4.N; dot at R3.N
ground((3.9,0))
.model QN NPN(IS=1e-14 BF=100 VAF=100)
.op
.tran 10u 3m
.PE

.PS
# Current-controlled sources read the current through V0, a 0 V
# ammeter in series with R1: i(v0) = 2 V / 1k = 2 mA. The CCCS
# (gain 3) pulls 6 mA out of Va through itself, so v(va) = -6 V across
# R2; the CCVS (500 ohm transresistance) sets v(vb) = 1 V across R3.
spice = 1
In: (0.3,2)
Vs: (1.5,2)
Va: (3.6,2)
Vb: (5.6,2)

V1: vsource(In, (0.3,0), DC 2)
R1: resistor(In, Vs, 1k)
V0: vsource(Vs, (1.5,0), DC 0)
F1: cccs((2.8,2), (2.8,0), V0 3)
R2: resistor(Va, (3.6,0), 1k)
H1: ccvs((4.8,2), (4.8,0), V0 500)
R3: resistor(Vb, (5.6,0), 1k)

line from F1.P to R2.P
line from H1.P to R3.P
line from V1.N to R3.N
dot at V0.N; dot at F1.N; dot at R2.N; dot at H1.N
ground(V1.N)
.op
.PE

.PS
# CMOS inverter (MOS1) driving 1 pF: a 0 -> 5 V input pulse flips the
# output rail to rail; no static current in either state.
spice = 1
M2: pmos((2,2.1), PMOD W=8u L=1u, "T₂")
M1: nmos((2,0.9), NMOD W=4u L=1u, "T₁")
Vin:  (1.2,1.5)
Vout: (M1.D.x,1.5)
Vdd:  (M2.S.x,2.7)

V1: vsource((0.3,1.5), (0.3,0), PULSE(0 5 5n 1n 1n 20n 50n), "G₁")
V2: vsource((6.2,2.7), (6.2,0), DC 5, "VDD")
C1: capacitor((4.2,1.5), (4.2,0), 1p)
line from M2.D to M1.D
line from M1.G to (Vin.x,M1.G.y) then to (Vin.x,M2.G.y) then to M2.G
line from V1.P to Vin
line from Vout to C1.P
line from M2.S to Vdd then to V2.P
line from M1.S to (M1.S.x,0)
line from V1.N to V2.N
dot at Vin; dot at Vout; dot at C1.P; dot at (M1.S.x,0); dot at C1.N
"in" above at (0.75,1.55)
line from C1.P to (4.8,1.5); circle rad 0.04 at (4.84,1.5)
"out" above at (4.84,1.55)
ground((1.2,0))
.model NMOD NMOS(LEVEL=1 VTO=0.7 KP=110u LAMBDA=0.04)
.model PMOD PMOS(LEVEL=1 VTO=-0.7 KP=50u LAMBDA=0.05)
.tran 0.1n 60n
.PE

.PS
# basic/dc2src.cir drawn: two sources summed into R3 through 1k and 2k
# (Millman: v(vx) = (2 v1 + v2)/5), then an inverting VCVS (x-1.5)
# into R4, swept over both sources. Card order kept; deck nodes 1 V1n,
# 2 V2n, 3 Vx, 4 Vout.
spice = 1
V1n:  (0.3,2)
V2n:  (2.9,2)
Vx:   (1.6,2)
Vout: (4.4,2)

V1: vsource(V1n, (0.3,0), dc 0)
V2: vsource(V2n, (2.9,0), dc 0)
R1: resistor(V1n, Vx, 1k)
R2: resistor(V2n, Vx, 2k)
R3: resistor(Vx, (1.6,0), 1k)
E1: vcvs(Vout, (4.4,0), (3.9,1.2), (3.9,0.8), -1.5)
R4: resistor((5.6,2), (5.6,0), 1k)

line from Vx to (1.6,2.6) then to (3.6,2.6) then to (3.6,1.2) then to E1.Cp
line from E1.Cn to (3.6,0.8) then to (3.6,0)
line from E1.P to R4.P
line from V1.N to R4.N
dot at Vx; dot at R3.N; dot at V2.N; dot at (3.6,0); dot at E1.N
ground((0.95,0))
.dc v1 0 1 0.25 v2 0 2 0.5
.PE

.PS
# basic/depsrc.cir drawn: the four dependent sources, each into its own
# load, all controlled by the 2 V source V1 — the VCVS (x2.5) and the
# VCCS (1 mS) by its voltage (top row, wired to it), the CCCS (x10) and
# the CCVS (-500 ohm) by its current i(v1) = -2 mA (bottom row, named
# in the card). Card order kept; deck nodes 1 Vc, 2 Ve, 3 Vg, 4 Vf,
# 5 Vh.
spice = 1
Vc: (0.3,5.6)
Ve: (2.8,5)
Vg: (5.2,5)
Vf: (1.5,2)
Vh: (4.2,2)

V1: vsource(Vc, (0.3,3), dc 2)
R1: resistor((1.1,5.6), (1.1,3), 1k)
E1: vcvs(Ve, (2.8,3), (2.3,4.2), (2.3,3.8), 2.5)
RE: resistor((4,5), (4,3), 1k)
G1: vccs((5.2,3), Vg, (4.7,4.2), (4.7,3.8), 1m)
RG: resistor((6.4,5), (6.4,3), 2k)
F1: cccs((1.5,0), Vf, v1 10, "10 i(V1)")
RF: resistor((2.5,2), (2.5,0), 100)
H1: ccvs(Vh, (4.2,0), v1 -500, "−500 i(V1)")
RH: resistor((5.2,2), (5.2,0), 1k)

line from V1.P to R1.P then to (4.4,5.6)
line from (2,5.6) to (2,4.2) then to E1.Cp
line from E1.Cn to (2,3.8) then to (2,3)
line from (4.4,5.6) to (4.4,4.2) then to G1.Cp
line from G1.Cn to (4.4,3.8) then to (4.4,3)
line from E1.P to RE.P
line from G1.N to RG.P
line from V1.N to RG.N
line from F1.N to RF.P
line from H1.P to RH.P
line from F1.P to RH.N
dot at R1.P; dot at (2,5.6)
dot at R1.N; dot at (2,3); dot at E1.N; dot at RE.N; dot at (4.4,3); dot at G1.P
dot at RF.N; dot at H1.N
ground((0.7,3)); ground((3.3,0))
.op
.PE

.PS
# basic/dfwd.cir drawn: two diodes of one model forward at 0.9 V — D1
# straight across the source with area 2 (twice IS, half RS), D2 in
# series with 50 ohm. Card order kept; deck nodes 1 Va, 2 Vk.
spice = 1
Va: (1.7,1.6)
Vk: (3,1.6)

V1: vsource((0.3,1.6), (0.3,0), dc 0.9)
D1: diode(Va, (1.7,0), dmod 2.0)
D2: diode(Va, Vk, dmod)
R2: resistor(Vk, (3,0), 50)

line from V1.P to Va
line from V1.N to R2.N
dot at Va; dot at D1.N
ground((1,0))
.model dmod d(is=2.5e-15 rs=4 n=1.2)
.op
.PE

.PS
# Berkeley's diffpair.cir drawn: an emitter-coupled pair Q1/Q2 with
# 10k collector loads, its tail current set by the Q3/Q4 mirror and
# Rbias (~0.56 mA). Elements are in the deck's card order, so the
# figure's netlist is the deck's with named nodes (1 In, 2 B1, 3 B2,
# 4 Vc1, 5 Vc2, 6 Tail, 7 Bias, 8 Vp, 9 Vn) and simulates identically.
spice = 1
In:   (0.3,2.5)
Bias: (1.95,1.42)
Vp:   (6.2,4)
Vn:   (6.2,0.3)

Vin: vsource(In, (0.3,1.7), sin(0 0.1 5meg) ac 1, "G₁")
Vcc: vsource(Vp, (6.2,3.2), 12, "VCC")
Vee: vsource(Vn, (6.2,1.1), -12, "VEE")
Q1: npn((2.9,2.5), qnl, "T₁")
Q2: npn((5.2,2.5), qnl, "T₂")
RS1: resistor((1.5,2.5), Q1.B, 1k)
RS2: resistor(Q2.B, (3.9,2.5), 1k)
RC1: resistor(Q1.C, (Q1.C.x,4), 10k)
RC2: resistor(Q2.C, (Q2.C.x,4), 10k)
Q3: npn((4.3,1), qnl, "T₃")
Q4: npn((2.6,1), qnl, "T₄")
Rbias: resistor((1.2,1.42), (1.2,2.3), 20k)

B1:   Q1.B
B2:   Q2.B
Vc1:  Q1.C
Vc2:  Q2.C
Tail: (Q3.C.x,1.7)

# input; the bias riser crosses it without a dot (no connection)
line from Vin.P to RS1.P
line from Rbias.N to (1.2,4) then to Vcc.P
# emitter-coupled tail and its current source
line from Q1.E to (Q1.E.x,1.7) then to (Q2.E.x,1.7) then to Q2.E
line from Q3.C to Tail
# mirror: Q4 diode-connected, its base/collector node drives Q3
line from Q3.B to (3.45,1) then to (3.45,1.42) then to Rbias.P
line from Q4.B to (1.95,1) then to Bias
line from Q4.E to (Q4.E.x,0.3) then to Vee.P
line from Q3.E to (Q3.E.x,0.3)
line from Vee.N to (6.6,1.1)
dot at Tail; dot at Q4.C; dot at Bias; dot at (Q3.E.x,0.3)
dot at RC1.N; dot at RC2.N
ground(Vin.N); ground(RS2.N); ground(Vcc.N); ground((6.6,1.1))
.model qnl npn(bf=80 rb=100 ccs=2pf tf=0.3ns tr=6ns cje=3pf cjc=2pf
+   va=50)
.tran 5ns 500ns
.PE

.PS
# basic/divider.cir drawn: a 1k/2k divider on a 5 V source beside a
# 1 mA current source into 4.7k (two independent loops, one ground).
# Card order kept; deck nodes 1 Vs, 2 Vdiv, 3 Vi.
spice = 1
Vs:   (0.3,2)
Vdiv: (1.5,2)
Vi:   (2.8,2)

V1: vsource(Vs, (0.3,0), dc 5)
R1: resistor(Vs, Vdiv, 1k)
R2: resistor(Vdiv, (1.5,0), 2k)
I1: isource((2.8,0), Vi, dc 1m)
R3: resistor((3.8,2), (3.8,0), 4.7k)

line from I1.N to R3.P
line from V1.N to R3.N
dot at R2.N; dot at I1.P
ground((0.9,0))
.op
.PE

.PS
# regress/jfet_amp.cir drawn: an n-JFET common-source stage (VTO -2,
# BETA 1.3m) with 4.7k drain load and 100 ohm source degeneration,
# driven through 10k; the 1.5 V sine pushes the gate into forward
# conduction on its crests. Card order kept; deck nodes 1 Vp, 5 In,
# 2 Vg, 3 Vd, 4 Vs.
spice = 1
Vp: (4.4,3.2)
In: (0.3,1.5)
Vg: (2.3,1.5)
Vd: (2.86,2.3)
Vs: (2.86,1.14)

Vdd: vsource(Vp, (4.4,0), dc 15, "VDD")
Vin: vsource(In, (0.3,0), dc 0 ac 1 sin(0 1.5 1meg), "G₁")
Rsig: resistor(In, Vg, 10k)
J1: njfet((2.7,1.5), jn, "T₁")
RD: resistor((2.86,3.2), Vd, 4.7k)
RS: resistor(Vs, (2.86,0), 100)

line from RD.N to J1.D
line from RD.P to Vdd.P
line from Vin.N to Vdd.N
line from Vd to (3.6,2.3); circle rad 0.04 at (3.64,2.3)
"out" above at (3.64,2.35)
dot at Vd; dot at RS.N
ground((1.5,0))
.model jn njf vto=-2 beta=1.3e-3 lambda=0.01 rd=20 rs=15 cgs=3p cgd=1.5p
+ pb=0.8 is=2e-14 b=0.95
.ac dec 10 1k 1g
.op
.tran 10n 3u
.PE

.PS
# basic/lck.cir drawn: at the operating point the coils are shorts and
# the capacitors open, so v(vl) = 3 V and the coupled secondary L2
# (k = 0.95) carries nothing: v(sec) = 0. Card order kept; deck nodes
# 1 Vs, 2 Vl, 3 Sec.
spice = 1
Vs:  (2.25,2.4)
Vl:  (2.25,1.2)
Sec: (3.25,2.4)

V1: vsource((0.3,2.4), (0.3,0), dc 3)
L1: inductor(Vs, Vl, 10m)
R1: resistor(Vl, (2.25,0), 150)
L2: inductor(Sec, (3.25,1.2), 20m)
K12: coupling(L1, L2, 0.95)
C1: capacitor((1.25,1.2), (1.25,0), 10u)
C2: capacitor((4.05,2.4), (4.05,0), 22u)
R3: resistor((4.85,2.4), (4.85,0), 1k)

line from V1.P to Vs
line from Vl to C1.P
line from L2.N to (3.25,0)
line from L2.P to R3.P
line from V1.N to R3.N
dot at Vl; dot at C2.P
dot at C1.N; dot at R1.N; dot at (3.25,0); dot at C2.N
ground((0.75,0))
.op
.PE

.PS
# regress/mes_amp.cir drawn: an n-MESFET (Statz, NMF) common-source
# stage with a 1k drain load and a 50 fF load capacitor, driven through
# 50 ohm by a 1 GHz sine biased at -0.5 V. Card order kept; deck nodes
# 1 Vp, 5 In, 2 Vg, 3 Vd.
spice = 1
Vp: (4.8,3.2)
In: (0.3,1.5)
Vg: (2.3,1.5)
Vd: (2.86,2.3)

Vdd: vsource(Vp, (4.8,0), dc 5, "VDD")
Vin: vsource(In, (0.3,0), dc -0.5 ac 1 sin(-0.5 1.5 1g), "G₁")
Rsig: resistor(In, Vg, 50)
Z1: nmes((2.7,1.5), zn, "T₁")
RL: resistor((2.86,3.2), Vd, 1k)
CL: capacitor((3.7,2.3), (3.7,0), 50f)

line from RL.N to Z1.D
line from RL.P to Vdd.P
line from Vd to CL.P then to (4.1,2.3); circle rad 0.04 at (4.14,2.3)
"out" above at (4.14,2.35)
line from Z1.S to (2.86,0)
line from Vin.N to Vdd.N
dot at Vd; dot at (2.86,0); dot at CL.N
ground((1.5,0))
.model zn nmf vto=-1.8 beta=3e-3 b=0.3 alpha=2.5 lambda=0.05 rd=5 rs=5
+ cgs=1p cgd=0.2p pb=0.8
.ac dec 10 1meg 100g
.tran 10p 4n
.PE

.PS
# regress/mos3_inv.cir drawn: two level-3 CMOS inverters in cascade
# (T₁/T₂ drive T₃/T₄, 50f and 100f loads) and, on the right, a
# self-biased level-3 amplifier T₅ — 200k drain-to-gate feedback,
# 500 ohm source degeneration with the bulk on ground (a four-terminal
# MOS), 10k load. Card order kept; deck nodes 1 Vp, 2 In, 3 Out1,
# 4 Out2, 5 Ain, 6 Vg, 7 Vd, 8 Vs.
spice = 1
maxpswid = 12
Vp:   (11.2,3.1)
In:   (1.2,1.5)
Out1: (2.16,1.5)
Out2: (4.56,1.5)
Ain:  (6.8,1.2)
Vg:   (7.8,1.2)
Vd:   (8.96,2)
Vs:   (8.96,0.84)

Vdd: vsource(Vp, (11.2,0), dc 3.3, "VDD")
Vin: vsource((0.3,1.5), (0.3,0), dc 0 pulse(0 3.3 2n 1n 1n 8n 20n), "G₁")
MN1: nmos((2,0.9), n3 l=1u w=4u ad=8p as=8p pd=12u ps=12u, "T₁")
MP1: pmos((2,2.1), p3 l=1u w=10u ad=20p as=20p pd=24u ps=24u, "T₂")
C3: capacitor((3.2,1.5), (3.2,0), 50f)
MN2: nmos((4.4,0.9), n3 l=1u w=4u ad=8p as=8p pd=12u ps=12u, "T₃")
MP2: pmos((4.4,2.1), p3 l=1u w=10u ad=20p as=20p pd=24u ps=24u, "T₄")
C4: capacitor((5.6,1.5), (5.6,0), 100f)
Vac: vsource(Ain, (6.8,0), dc 0 ac 1, "G₂")
Cin: capacitor(Ain, Vg, 10p)
RF: resistor(Vd, (7.8,2), 200k)
MN3: nmos4((8.8,1.2), n3 l=2u w=20u ad=40p as=40p pd=44u ps=44u, "T₅")
RS3: resistor(Vs, (8.96,0), 500)
RL: resistor((8.96,3.1), Vd, 10k)
C7: capacitor((10.3,2), (10.3,0), 0.2p)

# the two inverters
line from Vin.P to In
line from MN1.G to (1.2,0.9) then to (1.2,2.1) then to MP1.G
line from MP1.D to MN1.D
line from Out1 to C3.P then to (3.6,1.5)
line from MN2.G to (3.6,0.9) then to (3.6,2.1) then to MP2.G
line from MP2.D to MN2.D
line from Out2 to C4.P
line from MN1.S to (2.16,0)
line from MN2.S to (4.56,0)
# the amplifier
line from Cin.N to MN3.G
line from RF.N to Vg
line from MN3.D to Vd then to C7.P
line from MN3.B to (9.4,1.2) then to (9.4,0)
# rails
line from MP1.S to (2.16,3.1) then to Vp
line from MP2.S to (4.56,3.1)
line from Vin.N to Vdd.N
dot at In; dot at Out1; dot at C3.P; dot at (3.6,1.5); dot at Out2
dot at Vg; dot at Vd
dot at (4.56,3.1); dot at RL.P
dot at (2.16,0); dot at C3.N; dot at (4.56,0); dot at C4.N; dot at Vac.N
dot at RS3.N; dot at (9.4,0); dot at C7.N
ground((0.75,0))
.model n3 nmos level=3 vto=0.6 nsub=4e16 tox=1.5e-8 xj=0.15u ld=0.05u u0=450
+ theta=0.06 eta=0.2 delta=0.6 vmax=1.6e5 kappa=0.4 nfs=6e11 rsh=15
+ cj=4e-4 mj=0.45 cjsw=3e-10 mjsw=0.3 cgso=2e-10 cgdo=2e-10 cgbo=1e-10
.model p3 pmos level=3 vto=-0.7 nsub=3e16 tox=1.5e-8 xj=0.2u ld=0.06u u0=180
+ theta=0.05 eta=0.15 delta=0.5 kappa=0.6 nfs=4e11 rsh=25
+ cj=5e-4 mj=0.5 cjsw=3.5e-10 mjsw=0.33 cgso=2.5e-10 cgdo=2.5e-10 cgbo=1e-10
.ac dec 10 10k 10g
.op
.tran 0.1n 40n
.PE

.PS
# Body effect: M1 (MOS1, VTO 0.7, GAMMA 0.5, PHI 0.6) with its bulk on
# V3 instead of the source. With VBS = -2 V the threshold rises to
# 0.7 + 0.5 (sqrt(2.6) - sqrt(0.6)) = 1.119 V, and the saturated drain
# current at VGS = 2 V falls from 0.845 mA to 0.388 mA. The .dc sweep
# walks VBS from 0 to -3 V.
spice = 1
M1: nmos4((2,1), NMOD W=10u L=1u)
Vg:  (0.6,1)
Vd:  M1.D
Vb:  (3.2,1)
Vdd: (4.6,2.4)

V1: vsource(Vdd, (4.6,0), DC 5)
V2: vsource(Vg, (0.6,0), DC 2)
V3: vsource(Vb, (3.2,0), DC -2)
RD: resistor((M1.D.x,2.4), M1.D, 1k)

line from V2.P to M1.G
line from M1.B to V3.P
line from RD.P to V1.P
line from M1.S to (M1.S.x,0)
line from V2.N to V1.N
dot at (M1.S.x,0); dot at V3.N
ground((1.3,0))
.model NMOD NMOS(LEVEL=1 VTO=0.7 KP=100u GAMMA=0.5 PHI=0.6)
.op
.dc V3 0 -3 -1
.PE

.PS
# Berkeley's mos6inv.cir drawn: four NDINV cells in a chain, each an
# instance of the subcircuit in mos6inv_sub.sub (pulled in by
# `.include`, with the deck's six model cards) through the generic
# `subckt6` box. Pins in `.SUBCKT NDINV 10 11 21 31 41 100` order: 1 in
# (left), 2-4 the inner stage outputs (bottom, brought out to test
# points as the deck does, so each is a one-pin net), 5 out (right),
# 6 vdd (top). Card order kept (XNDINV1-4, VDD, VIN); deck nodes 1 In,
# 2-5 N2-N5, 11-43 N11-N43, 100 Vp.
spice = 1
maxpswid = 12
In: (0.9,1.5)
N2: (2.1,1.5)
N3: (3.9,1.5)
N4: (5.7,1.5)
N5: (7.5,1.5)
Vp: (1.5,2.3)
N11: (1.2,1.1)
N12: (1.5,1.1)
N13: (1.8,1.1)
N21: (3,1.1)
N22: (3.3,1.1)
N23: (3.6,1.1)
N31: (4.8,1.1)
N32: (5.1,1.1)
N33: (5.4,1.1)
N41: (6.6,1.1)
N42: (6.9,1.1)
N43: (7.2,1.1)

XNDINV1: subckt6(In, N11, N12, N13, N2, (1.5,1.9), NDINV)
XNDINV2: subckt6((2.7,1.5), N21, N22, N23, N3, (3.3,1.9), NDINV)
XNDINV3: subckt6((4.5,1.5), N31, N32, N33, N4, (5.1,1.9), NDINV)
XNDINV4: subckt6((6.3,1.5), N41, N42, N43, N5, (6.9,1.9), NDINV)
VDD: vsource((8.7,2.3), (8.7,0), 5, "VDD")
VIN: vsource((0.3,1.5), (0.3,0), DC 0 PWL(0 0 2N 5), "G₁")

line from VIN.P to XNDINV1.P1
line from XNDINV1.P5 to XNDINV2.P1
line from XNDINV2.P5 to XNDINV3.P1
line from XNDINV3.P5 to XNDINV4.P1
line from XNDINV4.P5 to (7.9,1.5); circle rad 0.04 at (7.94,1.5)
"out" above at (7.94,1.55)
line from Vp to VDD.P
line from XNDINV1.P6 to (XNDINV1.P6.x,2.3)
line from XNDINV2.P6 to (XNDINV2.P6.x,2.3)
line from XNDINV3.P6 to (XNDINV3.P6.x,2.3)
line from XNDINV4.P6 to (XNDINV4.P6.x,2.3)
dot at (3.3,2.3); dot at (5.1,2.3); dot at (6.9,2.3)
line from XNDINV1.P2 to (1.2,0.84); circle rad 0.04 at (1.2,0.8); "11" below at (1.2,0.76)
line from XNDINV1.P3 to (1.5,0.84); circle rad 0.04 at (1.5,0.8); "12" below at (1.5,0.76)
line from XNDINV1.P4 to (1.8,0.84); circle rad 0.04 at (1.8,0.8); "13" below at (1.8,0.76)
line from XNDINV2.P2 to (3,0.84); circle rad 0.04 at (3,0.8); "21" below at (3,0.76)
line from XNDINV2.P3 to (3.3,0.84); circle rad 0.04 at (3.3,0.8); "22" below at (3.3,0.76)
line from XNDINV2.P4 to (3.6,0.84); circle rad 0.04 at (3.6,0.8); "23" below at (3.6,0.76)
line from XNDINV3.P2 to (4.8,0.84); circle rad 0.04 at (4.8,0.8); "31" below at (4.8,0.76)
line from XNDINV3.P3 to (5.1,0.84); circle rad 0.04 at (5.1,0.8); "32" below at (5.1,0.76)
line from XNDINV3.P4 to (5.4,0.84); circle rad 0.04 at (5.4,0.8); "33" below at (5.4,0.76)
line from XNDINV4.P2 to (6.6,0.84); circle rad 0.04 at (6.6,0.8); "41" below at (6.6,0.76)
line from XNDINV4.P3 to (6.9,0.84); circle rad 0.04 at (6.9,0.8); "42" below at (6.9,0.76)
line from XNDINV4.P4 to (7.2,0.84); circle rad 0.04 at (7.2,0.8); "43" below at (7.2,0.76)
line from VIN.N to VDD.N
ground((4.2,0))
.include mos6inv_sub.sub
.TRAN 0.5N 150N
.PRINT TRAN V(In) V(N2) V(N3) V(N4) V(N5)
.PRINT TRAN V(N11) V(N12) V(N13) V(N41) V(N42) V(N43)
.OPTIONS ACCT
.PE

.PS
# Inverting amplifier: gain -R2/R1 = -10 around an ideal op-amp
# (corpus/pic/opamp_ideal.sub, pulled in by `.include` next to this file).
spice = 1
X1: opamp((3,1), opamp_ideal)
Vin:  (0.3,1.175)
Vm:   (1.8,1.175)
Vout: (3.8,1)

V1: vsource(Vin, (0.3,0), DC 0.5)
R1: resistor(Vin, Vm, 1k)
R2: resistor((1.8,2), (3.8,2), 10k)
line from Vm to X1.Inm
line from Vm to R2.P
line from R2.N to Vout
line from X1.Out to Vout then to (4.3,1); circle rad 0.04 at (4.34,1)
"out" ljust at (4.4,1)
line from X1.Inp to (X1.Inp.x,0)
line from V1.N to (X1.Inp.x,0)
dot at Vm; dot at Vout
ground((1.4,0))
.include opamp_ideal.sub
.dc V1 -1 1 0.25
.PE

.PS
# RC low-pass driven by a 0 -> 5 V step; tau = R1*C1 = 1 ms.
spice = 1
Vin: (0,1.5); Vout: (2.5,1.5)
V1: vsource(Vin, (0,0), PULSE(0 5 0 1u 1u 10m 20m), "G₁")
R1: resistor(Vin, Vout, 1k)
C1: capacitor(Vout, (2.5,0), 1u)
line from V1.N to C1.N
ground((1.25,0))
dot at Vin; dot at Vout
"in" above at Vin + (0,0.05)
"out" above at Vout + (0,0.05)
.tran 20u 5m
.PE

.PS
# Berkeley's rca3040.cir drawn: the RCA CA3040 wideband amplifier.
# Emitter followers T₁/T₂ drive the pair T₃/T₄, cascoded by T₅/T₆
# (their bases held by the diode string T₇/T₈ under R7); T₉ sinks the
# tail current set by R4/R5/R3, and T₁₀/T₁₁ buffer the two collector
# loads. Elements are in the deck's card order (pins are coordinates,
# so no transistor is referenced before its card), and the figure's
# netlist is the deck's with named nodes (1 In, 2 Vp, 3 Vn, 5 Ba,
# 6 Bb, 7 Tail, 8 Bias, 9 Vt, 10 Ca, 11 Cb, 12 Vcas, 13 Vd, 14 Oa,
# 15 Ob, 16 Out, 17 Outb, 30 B1, 31 B2). Two wires cross without a dot
# (no connection): the cascode bias into T₆ and T₂'s emitter into T₄,
# each over the T₃–T₅ / T₄–T₆ link. The deck's 3-node Q cards keep
# the substrate (CCS) on ground, so the plain npn symbol is used.
spice = 1
maxpswid = 12
In:   (0.2,4.4)
B1:   (1.52,4.4)
B2:   (8.92,4.4)
Vp:   (10.6,8.4)
Vn:   (10.6,0)
Ba:   (2.16,3.2)
Bb:   (9.56,3.85)
Tail: (6.16,2.3)
Bias: (4.4,1.6)
Vt:   (6.16,1.18)
Ca:   (4.76,3.8)
Cb:   (7.56,4.1)
Vcas: (3.4,7)
Vd:   (3.4,5.9)
Oa:   (4.76,6.6)
Ob:   (7.56,6.6)
Out:  (8.56,6.18)
Outb: (5.76,6.18)

.ac dec 10 1 10ghz
.dc vin -0.25 0.25 0.005
.tran 2.0ns 200ns
Vin: vsource(In, (0.2,3.2), sin(0 0.1 50meg 0.5ns) ac 1, "G₁")
Vcc: vsource(Vp, (10.6,7.2), 15.0, "VCC")
Vee: vsource(Vn, (10.6,1), -15.0, "VEE")
RS1: resistor(B1, In, 1k)
RS2: resistor(B2, (7.95,4.4), 1k)
R1: resistor(Ba, (2.16,0), 4.8k)
R2: resistor(Bb, (9.56,0), 4.8k)
R3: resistor(Vt, (6.16,0), 811)
R4: resistor(Bias, (4.4,0), 2.17k)
R5: resistor((3.6,1.6), (3.6,0.6), 820)
R6: resistor((4.76,8.4), Oa, 1.32k)
R7: resistor((3.4,8.4), Vcas, 4.5k)
R8: resistor((7.56,8.4), Ob, 1.32k)
R9: resistor(Out, (8.56,5.3), 5.25k)
R10: resistor(Outb, (5.76,5.3), 5.25k)
Q1: npn((2,4.4), qnl, "T₁")
Q2: npn((9.4,4.4), qnl, "T₂")
Q3: npn((4.6,3.2), qnl, "T₃")
Q4: npn((7.4,3.2), qnl, "T₄")
Q5: npn((4.6,4.8), qnl, "T₅")
Q6: npn((7.4,4.8), qnl, "T₆")
Q7: npn((3.24,6.4), qnl, "T₇")
Q8: npn((3.24,5.4), qnl, "T₈")
Q9: npn((6,1.6), qnl, "T₉")
Q10: npn((8.4,6.6), qnl, "T₁₀")
Q11: npn((5.6,6.6), qnl, "T₁₁")

# supply rails
line from Q1.C to (2.16,8.4) then to Vcc.P
line from Q11.C to (5.76,8.4)
line from Q10.C to (8.56,8.4)
line from Q2.C to (9.56,8.4)
line from R1.N to Vee.P
line from Vee.N to (11,1)
# input followers into the pair
line from Q1.E to Ba then to Q3.B
line from Q2.E to Bb then to (6.75,3.85) then to (6.75,3.2) then to Q4.B
# pair, cascode, tail
line from Q3.C to Q5.E
line from Q4.C to Q6.E
line from Q3.E to (4.76,2.3) then to (7.56,2.3) then to Q4.E
line from Q9.C to Tail
line from Q9.B to (3.6,1.6)
# cascode bias: the T₇/T₈ diode string
line from Q7.C to Vcas
line from Q7.B to (2.76,7) then to Vcas then to (4,7) then to (4,4.1) \
  then to (6.6,4.1) then to (6.6,4.8) then to Q6.B
line from (4,4.8) to Q5.B
line from Q7.E to Q8.C
line from Q8.B to (2.76,5.9) then to Vd
# collector loads into the output followers
line from Oa to Q5.C
line from Oa to Q11.B
line from Ob to Q6.C
line from Ob to Q10.B
dot at (3.4,8.4); dot at (4.76,8.4); dot at (5.76,8.4); dot at (7.56,8.4)
dot at (8.56,8.4); dot at (9.56,8.4)
dot at (4.4,0); dot at (6.16,0); dot at (9.56,0)
dot at Ba; dot at Bb; dot at Tail; dot at Bias; dot at Vcas; dot at Vd
dot at (4,4.8); dot at Oa; dot at Ob
ground(Vin.N); ground(RS2.N); ground(R5.N); ground(Q8.E)
ground(R9.N); ground(R10.N); ground(Vcc.N); ground((11,1))
.model qnl npn bf=80 rb=100 ccs=2pf tf=0.3ns tr=6ns cje=3pf
+ cjc=2pf va 50
.PE

.PS
# Half-wave rectifier with a reservoir capacitor: 10 V 60 Hz sine,
# load R1 || C1 (tau = 100 ms >> 16.7 ms period).
spice = 1
Vout: (1.75,1.5)
V1: acsource((0,1.5), (0,0), SIN(0 10 60))
D1: diode(V1.P, Vout, DMOD)
C1: capacitor(Vout, (1.75,0), 100u)
R1: resistor((3,1.5), (3,0), 1k)
line from Vout to R1.P
line from V1.N to R1.N
ground((0.9,0))
dot at Vout; dot at C1.N
"out" above at Vout + (0,0.05)
.model DMOD D(IS=1e-14 RS=0.5)
.tran 0.1m 50m
.PE

.PS
# Series RLC driven by a 1 V AC source, output across C1:
# f0 = 1/(2 pi sqrt(L1 C1)) = 1.59 kHz, Q = sqrt(L1/C1)/R1 = 5.
spice = 1
Vin: (0,1.5); Vout: (3,1.5)
V1: vsource(Vin, (0,0), AC 1)
R1: resistor(Vin, (1.5,1.5), 20)
L1: inductor(R1.N, Vout, 10m)
C1: capacitor(Vout, (3,0), 1u)
line from V1.N to C1.N
ground((1.5,0))
dot at Vout
"out" above at Vout + (0,0.05)
.ac dec 20 100 100k
.PE

.PS
# Berkeley's rtlinv.cir drawn: two cascaded RTL inverters. Elements
# are in the deck's card order, so the figure's netlist is the deck's
# with named nodes (1 In, 2 B1, 3 Out1, 4 B2, 5 Out2, 6 Vp) and
# simulates identically.
spice = 1
In:   (0.3,1.2)
B1:   (1.72,1.2)
Out1: (2.36,1.62)
B2:   (3.72,1.2)
Out2: (4.36,1.62)
Vp:   (5.2,3)

Vcc: vsource(Vp, (5.2,0.3), 5, "VCC")
Vin: vsource(In, (0.3,0.3), pulse(0 5 2ns 2ns 2ns 80ns), "G₁")
RB1: resistor(In, B1, 10k)
RC1: resistor((2.36,3), Out1, 1k)
Q1: npn((2.2,1.2), qnd, "T₁")
RB2: resistor(Out1, (3.4,1.62), 10k)
Q2: npn((4.2,1.2), qnd, "T₂")
RC2: resistor((4.36,3), Out2, 1k)

line from RC1.P to Vcc.P
line from RB2.N to (3.4,1.2) then to Q2.B
line from Q1.E to (Q1.E.x,0.3)
line from Q2.E to (Q2.E.x,0.3)
line from Vin.N to Vcc.N
dot at Out1; dot at RC2.P; dot at (Q1.E.x,0.3); dot at (Q2.E.x,0.3)
ground((1.2,0.3))
.model qnd npn(bf=50 rb=70 rc=40 ccs=2pf tf=0.1ns tr=10ns cje=0.9pf
+   cjc=1.5pf pc=0.85 va=50)
.dc vin 0.0 2.5 0.025
.tran 2ns 200ns
.PE

.PS
# Reflection on a mismatched line: a 1 V step from a matched 50 ohm
# source into a 50 ohm, 1 ns line ending in 150 ohm (Gamma = 0.5).
# The launched 0.5 V wave reaches the load at TD and doubles to
# 0.75 V there; the reflection is back at the input at 2 TD.
spice = 1
Vin:  (1.4,1.5)
Vend: (3.8,1.5)
V1: vsource((0,1.5), (0,0), PULSE(0 1 0 10p 10p 20n 40n), "G₁")
R1: resistor(V1.P, Vin, 50)
T1: tline(Vin, Vend, Z0=50 TD=1n)
R2: resistor(Vend, (3.8,0), 150)
line from T1.N1 to (T1.N1.x,0)
line from T1.N2 to (T1.N2.x,0)
line from V1.N to R2.N
dot at (T1.N1.x,0); dot at (T1.N2.x,0)
dot at Vin; dot at Vend
"in" above at Vin + (0,0.05)
"end" above at Vend + (0,0.05)
ground((1.2,0))
.tran 10p 5n
.PE

.PS
# basic/trpwl.cir drawn: a piecewise-linear source (G₁) and an
# exponential one (G₂), each into its own RC low-pass (tau = 100 ns
# both). Card order kept; deck nodes 1 In1, 2 Out1, 3 In2, 4 Out2.
spice = 1
In1:  (0.3,1.5)
Out1: (1.5,1.5)
In2:  (2.5,1.5)
Out2: (3.7,1.5)

V1: vsource(In1, (0.3,0), pwl(0 0 1u 1 2u 1 3u -1 5u 0), "G₁")
R1: resistor(In1, Out1, 1k)
C1: capacitor(Out1, (1.5,0), 100p)
V2: vsource(In2, (2.5,0), exp(0 2 0.5u 0.3u 2.5u 0.6u), "G₂")
R2: resistor(In2, Out2, 500)
C2: capacitor(Out2, (3.7,0), 200p)

line from V1.N to C2.N
dot at C1.N; dot at V2.N
ground((0.9,0))
.tran 0.02u 6u
.PE

.PS
# basic/trrlc.cir drawn: a damped 100 kHz sine (delay 2u, theta 2e4)
# into a series RLC (f0 = 100.7 kHz, Q = 3.2), output across C1. Card
# order kept; deck nodes 1 In, 2 Vr, 3 Vout.
spice = 1
In:   (0.3,1.5)
Vr:   (1.5,1.5)
Vout: (2.9,1.5)

Vin: vsource(In, (0.3,0), sin(0 1 100k 2u 2e4), "G₁")
R1: resistor(In, Vr, 200)
L1: inductor(Vr, Vout, 1m)
C1: capacitor(Vout, (2.9,0), 2.5n)

line from Vin.N to C1.N
dot at Vr; dot at Vout
ground((1.6,0))
.tran 0.05u 50u
.PE

.PS
# basic/truic.cir drawn: no source at all — .tran uic starts from the
# stored energy, C1 charged to 2 V and L1 carrying 1 mA, and the
# network rings down through R1 and R2. Card order kept; deck nodes
# 1 Vc, 2 Vl.
spice = 1
Vc: (1.1,2)
Vl: (2.5,2)

C1: capacitor((0.3,2), (0.3,0), 1u ic=2)
R1: resistor(Vc, (1.1,0), 1k)
L1: inductor(Vc, Vl, 1m ic=1m)
R2: resistor(Vl, (2.5,0), 50)

line from C1.P to R1.P
line from C1.N to R2.N
dot at Vc; dot at R1.N
ground((1.8,0))
.tran 2u 3m uic
.PE

.PS
# Double-tuned (coupled-resonator) band-pass: two 10u || 10n tanks
# (f0 = 503 kHz, Q = 31.6 with the 1k source and load) coupled by
# k = 0.1. kQ > 1, so the pair is overcoupled: two peaks near
# f0/sqrt(1 +- k) = 480 and 531 kHz, each at the matched-transfer
# limit |v(vout)| = 1/2.
spice = 1
In:   (0.3,2)
Pri:  (1.4,2)
Vout: (4.8,2)

V1: acsource(In, (0.3,0), AC 1)
RS: resistor(In, Pri, 1k)
C1: capacitor(Pri, (1.4,0), 10n)
L1: inductor((2.2,2), (2.2,0), 10u)
L2: inductor((3.2,2), (3.2,0), 10u)
K1: coupling(L1, L2, 0.1)
C2: capacitor((4,2), (4,0), 10n)
RL: resistor(Vout, (4.8,0), 1k)

line from C1.P to L1.P
line from L2.P to RL.P
line from V1.N to RL.N
dot at C1.P; dot at C2.P
dot at C1.N; dot at L1.N; dot at L2.N; dot at C2.N
ground(V1.N)
.ac lin 401 400k 650k
.PE

.PS
# Voltage-controlled sources in cascade: the 1:2 divider R1/R2 feeds a
# VCVS (gain 10, loaded by R3), whose output drives a VCCS (1 mS) into
# RL = 2k. Closed form: v(vx) = vin/2, v(vm) = 5 vin, v(vout) =
# -1m * 2k * v(vm) = -10 vin.
spice = 1
Vin:  (0.3,2)
Vx:   (1.6,2)
Vm:   (3,2)
Vout: (6.6,2)

V1: vsource(Vin, (0.3,0), DC 0)
R1: resistor(Vin, Vx, 1k)
R2: resistor(Vx, (1.6,0), 1k)
E1: vcvs(Vm, (3,0), (2.5,1.2), (2.5,0.8), 10)
R3: resistor((4.1,2), (4.1,0), 1k)
G1: vccs((5.5,2), (5.5,0), (5,1.2), (5,0.8), 1m)
RL: resistor(Vout, (6.6,0), 2k)

line from Vx to (2.1,2) then to (2.1,1.2) then to E1.Cp
line from E1.Cn to (2.1,0.8) then to (2.1,0)
line from E1.P to R3.P then to (4.6,2) then to (4.6,1.2) then to G1.Cp
line from G1.Cn to (4.6,0.8) then to (4.6,0)
line from G1.P to RL.P
line from V1.N to RL.N
dot at Vx; dot at R3.P
dot at R2.N; dot at (2.1,0); dot at E1.N; dot at R3.N; dot at (4.6,0); dot at G1.N
ground(V1.N)
.dc V1 -1 1 0.5
.PE

AC decade grid over a non-whole-decade span lands on FSTOP (ngspice)
* Regression: ngspice-47 (acan.c) recomputes the decade step as
* exp(ln(stop/start)/floor(log10(stop/start)*n)) whenever the span
* exceeds one decade, so the sweep ends exactly at FSTOP; the 3f5's
* 10^(1/n) agrees only on whole-decade spans. 10meg->2g spans 2.30
* decades: the grids differ at every point past the first without
* the ngspice form. Under one decade (and stop==start) the 3f5 step
* survives in both programs.
vin 1 0 dc 0 ac 1
r1 1 2 1k
c1 2 0 15.9p
r2 2 3 10k
l1 3 0 1u
.ac dec 10 10meg 2g
.end

BSIM1 common-source stage with source degeneration: harmonics in .disto
* Coverage: b1dset.c's Dderivs transcription of the BSIM1 drain current
* in saturation with vds < VDD (the quadratic Beta0 interpolation and
* its d_dummy quirk), body effect through the 1k source resistor
* (vbs swings), Von's Eta*vds taken with Eta constant, the 40/60
* charges (XPART absent) with b1dset.c's 1/15 saturation drain charge,
* reverse bulk junctions; 2nd and 3rd harmonics of b1disto.c against
* ngspice-47. (XPART=0 on the card would mean 0/100 in ngspice-47:
* the parameter is a flag there, set by its mere presence.)
vdd 5 0 5
vin 1 0 0 distof1 0.02
vbias 2 1 2.0
rg 2 3 10k
m1 4 3 7 6 nmos l=2u w=20u ad=40p as=40p pd=24u ps=24u
rd 5 4 10k
cl 4 0 0.2p
vbb 6 0 -1
rsrc 7 0 1k
.model nmos nmos
+ level=4 tox=3.00000e-2 vdd=5 temp=27
+ dl=7.97991e-1 dw=4.77402e-1
+ vfb=-1.0087 phi=7.96434e-1 k1=1.31191 k2=1.46640e-1
+ eta=-1.0027e-3 muz=5.34334e+2 u0=4.38497e-2 u1=-5.7332e-2
+ x2e=-7.6911e-4 x3e=7.86777e-4 x2mz=8.25434
+ mus=5.40612e+2 x2ms=-1.2992e+1 x3ms=-9.4035
+ x2u0=1.06821e-3 x2u1=-1.9209e-2 x3u1=7.76925e-3
+ n0=1.55 nb=0.09 nd=0.0
+ cgdo=2.70000e-10 cgso=2.70000e-10 cgbo=1.40000e-10
+ rsh=0 cj=2.75e-4 cjsw=1.90e-10 js=1.0e-8
+ pb=0.7 pbsw=0.8 mj=0.5 mjsw=0.33 wdf=0.0
.disto dec 10 1e3 1e10
.end

BSIM1 stage in inverse mode: intermodulation in .disto
* Coverage: b1dset.c in the inverse mode (drain and source swapped on
* the card, so vds < 0: the chain rule for the current and for the
* 0/100 (XPART=1) gate, bulk and drain charges), a forward-biased
* bulk-drain junction (vbb = +0.45 V over the 1k drain resistor, JS
* raised so it conducts) whose gbd term b1disto.c stamps from the GATE
* in the F1+F2/F1-F2 modes, and IM products f1+f2, f1-f2, 2f1-f2
* against ngspice-47.
vdd 5 0 5
vin 1 0 0 distof1 0.02 distof2 0.015
vbias 2 1 1.6
rg 2 3 10k
m1 8 3 4 6 nmos l=2u w=20u ad=60p as=40p pd=30u ps=24u
rd 5 4 10k
cl 4 0 0.2p
vbb 6 0 0.45
rsd 8 0 1k
.model nmos nmos
+ level=4 tox=3.00000e-2 vdd=5 temp=27
+ dl=7.97991e-1 dw=4.77402e-1
+ vfb=-1.0087 phi=7.96434e-1 k1=1.31191 k2=1.46640e-1
+ eta=-1.0027e-3 muz=5.34334e+2 u0=4.38497e-2 u1=-5.7332e-2
+ x2e=-7.6911e-4 x3e=7.86777e-4 x2mz=8.25434
+ mus=5.40612e+2 x2ms=-1.2992e+1 x3ms=-9.4035
+ x2u0=1.06821e-3 x2u1=-1.9209e-2 x3u1=7.76925e-3
+ n0=1.55 nb=0.09 nd=0.0
+ cgdo=2.70000e-10 cgso=2.70000e-10 cgbo=1.40000e-10 xpart=1
+ rsh=0 cj=2.75e-4 cjsw=1.90e-10 js=1.0e-2
+ pb=0.7 pbsw=0.8 mj=0.5 mjsw=0.33 wdf=0.0
.disto dec 10 1e3 1e10 0.9
.end

BSIM1 transient overlap caps use drawn W and effective L (b1ld.c)
* Regression: the transient load builds the gate overlap caps from the
* DRAWN width (gs/gd) and the EFFECTIVE length (gb), per b1ld.c, while
* b1temp.c's per-instance values (effective W, drawn L) feed only the
* AC load. Dune once used the b1temp.c values in both places. Here the
* gate pulse (device always cut off) couples through Cgdo onto a
* floating 1 fF drain node, and the stored plateau voltage measures
* the overlap cap directly: drawn vs effective W differs by ~24%.
m1 2 1 0 0 nmos l=2u w=2u ad=0.1p as=0.1p
c1 2 0 1f
rbias 3 2 1g
vdd 3 0 2
vin 1 0 pulse(-2 0 5ns 1ns 1ns 20ns 50ns)
.tran 0.5ns 40ns
.print tran v(1) v(2)
.model nmos nmos
+ level=4 tox=3.00000e-2 vdd=5 temp=27
+ dl=7.97991e-1 dw=4.77402e-1
+ vfb=-1.0087 phi=7.96434e-1 k1=1.31191 k2=1.46640e-1
+ eta=-1.0027e-3 muz=5.34334e+2 u0=4.38497e-2 u1=-5.7332e-2
+ x2e=-7.6911e-4 x3e=7.86777e-4 x2mz=8.25434
+ mus=5.40612e+2 x2ms=-1.2992e+1 x3ms=-9.4035
+ x2u0=1.06821e-3 x2u1=-1.9209e-2 x3u1=7.76925e-3
+ lvfb=-2.1402e-1 wvfb=3.44354e-1 lk1=3.23395e-1 wk1=-5.7698e-1
+ lk2=1.68585e-1 wk2=-1.8796e-1 leta=-9.4847e-3 weta=1.47316e-2
+ lu0=6.38105e-2 wu0=-6.1053e-2 lu1=1.01174 wu1=1.62706e-2
+ lx2e=9.62411e-3 wx2e=-3.7951e-3 lx3e=7.35448e-4 wx3e=-1.7796e-3
+ lx2mz=-2.4197e+1 wx2mz=1.95696e+1 lmus=6.21401e+2 wmus=-1.9190e+2
+ lx2ms=-6.4900e+1 wx2ms=4.29043e+1 lx3ms=1.18239e+2 wx3ms=-2.9747e+1
+ lx2u0=-8.0958e-3 wx2u0=4.03379e-3 lx2u1=-7.4573e-2 wx2u1=1.47520e-2
+ lx3u1=-1.0940e-1 wx3u1=-8.3353e-3
+ n0=1.55 nb=0.09 nd=0.0
+ cgdo=2.70000e-10 cgso=2.70000e-10 cgbo=1.40000e-10 xpart=1.0
+ rsh=35.0 cj=2.75e-4 cjsw=1.90e-10 js=1.0e-8
+ pb=0.7 pbsw=0.8 mj=0.5 mjsw=0.33 wdf=0.0
.end

One-BJT common-emitter amplifier: intermodulation in .disto
* Coverage: every Gummel-Poon nonlinearity bjtdset.c expands - the
* junction and leakage currents (ISE/ISC), Early (VAF/VAR), roll-off
* (IKF/IKR, the qb square root), the bias-dependent base resistance
* with IRB (the tan(z) chain and its power-series inversion), the
* transit time with XTF/VTF/ITF, excess phase (PTF: the delayed-vbe
* rotation of every kernel), the B-C capacitance split by XCJC (qbx
* on the external base) and the substrate capacitance - through the
* IM products f1+f2, f1-f2, 2f1-f2 against ngspice-47.
* Supply, input and substrate are Norton equivalents (a current
* source across a resistor) so every compared vector is a node
* voltage: the residual vs the golden is a uniform ~5e-5 relative
* (ngspice's physical constants move vt by 2.8e-5, and the
* coefficients go as Ic/vt^n), which a branch current crossing zero
* in one component would turn into a pointwise failure of the ruler.
icc 0 5 12
rcc 5 0 1
iin 0 1 0 distof1 2.5u distof2 2.5u
rs 1 0 1k
cin 1 3 10u
rb1 5 3 82k
rb2 3 0 15k
rc 5 4 4.7k
re 6 0 1k
ce 6 0 100u
q1 4 3 6 7 qmod
isub 7 0 2
rsub 7 0 1
.model qmod npn is=1e-15 bf=150 nf=1.01 vaf=60 ikf=20m ise=2e-14 ne=1.6
+ br=3 nr=1.02 var=20 ikr=5m isc=1e-14 nc=1.8
+ rb=150 irb=0.2m rbm=30 re=2 rc=15
+ cje=2p vje=0.8 mje=0.35 tf=0.4n xtf=2 vtf=4 itf=30m ptf=25
+ cjc=1.5p vjc=0.6 mjc=0.4 xcjc=0.6 tr=5n cjs=1p vjs=0.7 mjs=0.4
.disto dec 10 1e3 1e9 0.9
.end

One-PNP common-emitter amplifier: harmonics in .disto
* Coverage: the type factors of bjtdset.c (second-order coefficients
* carry BJTtype, third-order ones do not) on a PNP mirror of
* bjtdisto2.cir, through the 2nd and 3rd harmonics. CJS is 0 here:
* ngspice-47 defaults a PNP's substrate to LATERAL (cap on the base),
* the 3f5 and Dune put it on the collector (corpus/KNOWN_DIFFS.md).
* Norton-equivalent supplies, as in bjtdisto2.cir.
icc 5 0 12
rcc 5 0 1
iin 0 1 0 distof1 2.5u
rs 1 0 1k
cin 1 3 10u
rb1 5 3 82k
rb2 3 0 15k
rc 5 4 4.7k
re 6 0 1k
ce 6 0 100u
q1 4 3 6 7 qmod
isub 0 7 2
rsub 7 0 1
.model qmod pnp is=1e-15 bf=150 nf=1.01 vaf=60 ikf=20m ise=2e-14 ne=1.6
+ br=3 nr=1.02 var=20 ikr=5m isc=1e-14 nc=1.8
+ rb=150 irb=0.2m rbm=30 re=2 rc=15
+ cje=2p vje=0.8 mje=0.35 tf=0.4n xtf=2 vtf=4 itf=30m ptf=25
+ cjc=1.5p vjc=0.6 mjc=0.4 xcjc=0.6 tr=5n
.disto dec 10 1e3 1e9
.end

B source, AC: the operating-point derivatives as small-signal stamps
* Coverage: asrcacld.c (derivatives stored at MODEINITSMSIG), V= and
* I= forms, v(a,b), i(vsrc), and the f^g derivative with a variable
* exponent (the 3f5 writes ln f' where ngspice has ln f).
v1 1 0 dc 0.6 ac 1
r1 1 2 1k
b1 2 0 i=1e-14*(exp(v(2)/0.0258)-1)
c2 2 0 10p
b2 3 0 v=10*tanh(v(2))+v(2)^2
r3 3 4 1k
c4 4 0 1n
vx 4 5 dc 0
r5 5 0 1k
b3 6 0 v=1k*i(vx)*v(2)+v(3,4)
r6 6 0 1k
b4 0 7 i=1m*v(3,4)^2+1m*(v(2)+1)^v(1)
r7 7 0 1k
c7 7 0 2n
.ac dec 10 1k 1g
.end

B source, DC: the 3f5 expression functions and v()/i() references
* Coverage: ptfuncs.c functions on both signs of the swept v(1),
* v(a,b), i(vsrc), the e/pi constants, a constant V= source (the
* branch row the 3f5 leaves empty) and a nonlinear I= load that
* Newton has to solve (no limiting, as in asrcload.c).
v1 1 0 dc 0
v2 2 0 dc 1.5
r1 1 0 1k
b1 3 0 v=v(1)*v(2)+sin(v(1))-cos(v(2))/2+atan(v(1))+tanh(2*v(1))
r3 3 0 1k
b2 4 0 v=exp(v(1))+sqrt(v(2))+ln(v(2)+0.5)+abs(v(1)-0.25)+uramp(v(1))+u(v(1)-0.05)
r4 4 0 1k
b3 0 5 i=1m*v(1,2)^2+2*i(v1)+0.5m*sinh(v(1))-0.1m*cosh(v(1))
r5 5 0 1k
b4 6 0 v=asin(v(1)/2)+acos(v(1)/3)+asinh(v(1))+acosh(v(2)+2)+atanh(v(1)/2)+tan(v(1)/2)
r6 6 0 1k
b5 7 0 v=2*pi-e+sgn(v(1))+v(1)^2
r7 7 0 1k
vx 8 9 dc 0
r8 9 0 1k
b6 8 0 v=2^v(2)+(v(2)+1)^v(1)
b7 10 0 i=1e-14*(exp(v(10)/0.0258)-1)-0.1*i(vx)
r10 1 10 2k
b8 11 0 v=2*pi-e
r11 11 0 1k
.dc v1 -1 1 0.05
.end

B source comparator: u() and sgn() jump inside a timestep
* Coverage: no corpus deck made a B source jump (bsrc_tran multiplies
* its sgn() by a factor that vanishes with the argument). A 0 -> 5 -> 0
* triangle of 1 ms crosses b1's reference (3.05 V, at 0.305 ms and
* 0.695 ms) and b2's (2.05 V, at 0.205 ms and 0.795 ms) between the
* 20 us points of the .tran grid; b3 has the same sgn() times a
* factor that is zero there, and does not jump.
v1 1 0 pwl(0 0 0.5m 5 1m 0)
r1 1 0 1k
vref 3 0 3.05
r3 3 0 1k
b1 2 0 v=5*u(v(1)-v(3))
r2 2 0 1k
b2 0 4 i=1m*sgn(v(1)-2.05)
r4 4 0 1k
b3 5 0 v=(v(1)-2.05)*sgn(v(1)-2.05)
r5 5 0 1k
.tran 20u 1m
.end

B source, transient: expressions of time-varying nodes and branch currents
* Coverage: V= and I= sources driven by a sine, with a reactive load
* and an i() reference, through the transient Newton (asrcload.c).
v1 1 0 dc 0 sin(0 1 1meg)
r1 1 0 1k
b1 2 0 v=0.5*v(1)^2+0.1*abs(v(1))+0.2
r2 2 3 1k
c3 3 0 100p
b2 0 4 i=1m*tanh(2*v(3))+0.5*i(v1)
r4 4 0 1k
c4 4 0 50p
b3 5 0 v=uramp(v(1)-0.2)*(1+v(4))
r5 5 0 1k
l5 5 6 10u
r6 6 0 100
b4 7 0 i=1m*(v(7)-0.3)^2*sgn(v(7)-0.3)+0.2*i(v1)
r7 2 7 1k
.tran 10n 3u
.end

Semiconductor capacitors: C model CJ/CJSW geometry and DEFW
* Coverage: no corpus deck has a C model. captemp.c (3f5): with no
* value, C = CJ*(W-NARROW)*(L-NARROW) + 2*CJSW*((L-NARROW)+(W-NARROW)),
* W defaulting to DEFW (10u in the code; spice.txt documents 1u). The
* .ac reads each capacitance off an RC low-pass (corner ~1/(2*pi*R*C)).
* c1: L and W given. c2: L only (W = DEFW). c3: explicit value on a
* model card (value wins). NARROW stays 0: ngspice-47 subtracts SHORT
* from L instead, corpus/KNOWN_DIFFS.md.
v1 1 0 dc 0 ac 1
r1 1 2 10k
c1 2 0 cpoly l=100u w=50u
r2 1 3 10k
c2 3 0 cmet l=80u
r3 1 4 10k
c3 4 0 2p cpoly
.model cpoly c cj=3e-4 cjsw=2e-10
.model cmet c (cj=1e-4 cjsw=5e-11 defw=20u)
.ac dec 5 100k 100meg
.end

Current-controlled switch: W cards keyed by a separate control loop
* Coverage: no corpus deck has a W card. vi drives 0 -> 5 mA -> 0 through
* the sense source vsense in its own loop; w1 (IT=2.4m, IH=0.9m: closes
* above 3.3 mA, opens below 1.5 mA) charges c3 through RON and lets it
* bleed through rl1 when open, like a relay contact. w5 watches the
* mirrored loop (vsense2 carries 5 mA - i(vsense)), so the rising .dc
* also falls through a window. w2/w3 share a model whose window
* (-0.6m..5.4m) contains the whole control range: CSWload (ngspice)
* holds the state of the last *accepted* point (state1) inside the
* window, which is zero in the operating point, so w2 opens despite its
* ON hint (the 3f5 and SWload keep it closed). w4 has a negative IH.
vi 10 0 dc 0 pwl(0 0 1m 5 2m 0)
rctl 10 11 1k
vsense 11 0 dc 0
vo 12 0 dc 5
e1 13 12 10 0 -1
rctl2 13 14 1k
vsense2 14 0 dc 0
vdd 2 0 dc 10
w1 2 3 vsense wmod
rl1 3 0 1k
c3 3 0 100n
w2 2 4 vsense wwin on
rl2 4 0 1k
w3 2 5 vsense wwin off
rl3 5 0 1k
w4 2 6 vsense wneg
rl4 6 0 1k
w5 2 7 vsense2 wmod
rl5 7 0 1k
.model wmod csw it=2.4m ih=0.9m ron=10 roff=1e6
.model wwin csw it=2.4m ih=3m ron=100 roff=1e5
.model wneg csw it=2.4m ih=-0.7m ron=50 roff=2e5
.dc vi 0 5 0.2
.tran 20u 2m
.end

DC sweep of the circuit temperature: .dc temp nested under a source
* Coverage: the 3f5 DCtrCurv sweeps only V/I sources; ngspice-47
* (dctrcurv.c TEMP_CODE) also takes `temp`, re-running CKTtemp at each
* point (corpus/KNOWN_DIFFS.md). Inner level temp (-25..125 C), outer
* level v1. The diode, the BJT and the TC resistor follow the circuit
* temperature; rfix has an instance temp= and must not move; the scale
* vector is ngspice's `temp-sweep`.
v1 1 0 dc 1
r1 1 2 rtc l=20u w=2u
d1 2 0 dmod
rfix 1 3 rtc l=20u w=2u temp=27
q1 3 3 0 qmod
v2 4 0 dc 5
rc 4 5 2k
q2 5 3 0 qmod
.model rtc r rsh=100 tc1=3e-3 tc2=1e-5
.model dmod d is=1e-14 n=1.05 eg=1.11 xti=3
.model qmod npn is=1e-16 bf=120 xtb=1.5
.dc temp -25 125 25 v1 1 3 1
.end

Diode reverse breakdown from leakage to high current
* Coverage: the breakdown match of diotemp.c (xbv from BV/IBV) and the
* breakdown branch of dioload.c, swept from leakage through the knee
* to ~1.5 A. Two corrections of the 3f5 that ngspice-47 carries
* (corpus/KNOWN_DIFFS.md): dn has N=1.47, and the 3f5 matches xbv with
* plain vt while its load uses N*vt (ngspice: NBV*vt, NBV defaults to
* N), so the 3f5 knee sits (N-1)*vt*ln(IBV/IS) = 0.397 V higher; da
* has AREA=10, and the 3f5 matches the per-area saturation current
* against the absolute IBV (ngspice: IS*AREA against IBV), shifting
* the knee by vt*ln(10) = 60 mV. d3 is the same model without area:
* ngspice-47 rejects a model referenced only with a positional area.
* BV is small on purpose: at BV=50 the node test (reltol*50 V = 50 mV)
* exceeds N*vt, and ngspice's Newton stops off the curve by up to
* 0.18 V (path-dependent; see docs/dune-core.md, diode breakdown).
v1 1 0 dc 0
r1 1 2 10
d1 0 2 dn
r2 1 3 10
d2 0 3 da 10
r3 1 4 10
d3 0 4 da
.model dn d(is=6.79e-18 n=1.47 bv=5)
.model da d(is=1e-14 bv=5 ibv=1e-4)
.dc v1 0 20 0.25
.end

Diode noise: RS thermal, junction shot and flicker in .noise
* Coverage: dionoise.c in its ngspice-47 form - the RS thermal source
* between the anode and its internal node, shot noise of the junction
* current, KF*|Id|^AF/f flicker, and the three sidewall vectors
* (_rsw/_idsw/_1overfsw) ngspice always names, zero without RSW. d2
* has area 2 (RS conductance and current both scale) and sits in the
* signal path to the output, so its generators see a nontrivial
* transfer; d1 shunts the input node. TT and CJO shape the band.
vin 1 0 dc 0 ac 1
rin 1 2 10k
ib 0 2 dc 200u
d1 2 0 dn
d2 2 3 dn 2
rl 3 0 2k
.model dn d is=1e-14 rs=25 n=1.2 tt=5n cjo=2p kf=1e-14 af=1.2
.noise v(3) vin dec 10 1 1g 1
.end

Instance DTEMP= (ngspice-47) in the operating point
* Coverage: ngspice-47's instance DTEMP (res.c, dio.c, bjt.c,
* jfet.c, mos1.c, mos2.c, mos3.c, mos6.c; the 3f5 has no DTEMP): an
* instance without TEMP= runs at CKTtemp + DTEMP (*temp.c: "if
* (!tempGiven) temp = CKTtemp + dtemp"), so with .options temp=50
* every device below sits at its own temperature. rboth and dboth
* carry TEMP= and DTEMP= together: TEMP= wins and DTEMP is dropped
* (restemp.c zeroes RESdtemp with "Instance temperature specified,
* dtemp ignored"; the semiconductors simply never read it). Each
* device hangs off its own source, so every current is a separate
* branch vector; the JFET gate is forward biased so its IS(T) shows
* (the 3f5 JFET drain current itself has no temperature dependence).
.options temp=50
v1 1 0 dc 1
r1 1 0 rtc 1k dtemp=40
v2 2 0 dc 1
r2 2 0 rtc 1k
v3 3 0 dc 1
rboth 3 0 rtc 1k temp=0 dtemp=40
v4 4 0 dc 0.6
d1 4 0 dm dtemp=-60
v5 5 0 dc 0.6
dboth 5 0 dm temp=100 dtemp=-60
vb6 6 0 dc 0.68
vc6 16 0 dc 3
q6 16 6 0 qn dtemp=35
vg7 7 0 dc 0.55
vd7 17 0 dc 3
j7 17 7 0 jn dtemp=-45
vg8 8 0 dc 2
vd8 18 0 dc 3
m8 18 8 0 0 nm1 l=4u w=20u dtemp=60
vg9 9 0 dc 2
vd9 19 0 dc 3
m9 19 9 0 0 nm2 l=4u w=10u dtemp=-40
vg10 10 0 dc 2
vd10 20 0 dc 3
m10 20 10 0 0 nm3 l=4u w=10u dtemp=25
vg11 11 0 dc 2
vd11 21 0 dc 3
m11 21 11 0 0 n6 l=3u w=10u dtemp=-70
.model rtc r tc1=3e-3 tc2=2e-5
.model dm d is=1e-14 n=1.05 rs=5 xti=3 eg=1.11
.model qn npn is=1e-16 bf=120 ise=1e-14 ne=1.6 isc=1e-15 rb=100 re=2
+ vaf=60 xtb=1.5
.model jn njf vto=-2 beta=0.4e-3 lambda=0.02 rd=30 rs=20 is=1e-14
.model nm1 nmos level=1 vto=0.8 kp=50u lambda=0.02 phi=0.65 gamma=0.4
+ tpg=1 nsub=2e15 tox=5e-8
.model nm2 nmos level=2 vto=0.7 tox=40n nsub=1e16 uo=600 lambda=0.02
.model nm3 nmos level=3 vto=0.7 tox=30n nsub=1e16 uo=500 theta=0.1
.model n6 nmos level=6 tpg=1 kc=3.8921e-05 nc=1.1739 kv=0.91602 nv=0.87225
+ lambda0=0.013333 lambda1=0.0046901 vt0=0.69486 gamma=0.60309 phi=1
+ tox=1.98e-08 ld=0.1u nsub=5e16 nss=0
.op
.end

JFET, MESFET and switch noise in one cascade
* Coverage: jfetnoi.c (ngspice-47, default NLEV=2) and mesnoise.c - RD
* and RS thermal, channel thermal 4kT*(2/3)|gm|, KF*|Id|^AF/f flicker -
* and the single thermal generator of a closed S switch (swnoise.c,
* vector onoise_s1) in series with the MESFET load. The JFET stage
* drives the MESFET gate through a coupling capacitor; the MESFET gate
* is biased through 100k from its own source.
vdd 1 0 dc 15
vin 2 0 dc 0 ac 1
j1 3 2 4 jn 2
rd1 1 3 4.7k
rs1 4 0 100
cs1 4 0 10u
c12 3 6 1u
rg2 6 7 100k
vg2 7 0 dc -0.5
z1 8 6 0 zn
s1 9 8 10 0 sw1
rl2 11 9 1k
vdd2 11 0 dc 5
vctl 10 0 dc 5
.model jn njf vto=-2 beta=1.3e-3 lambda=0.01 rd=20 rs=15 cgs=3p cgd=1.5p
+ kf=1e-17 af=1.1
.model zn nmf vto=-1.8 beta=3e-3 b=0.3 alpha=2.5 lambda=0.05 rd=5 rs=5
+ cgs=1p cgd=0.2p kf=1e-16 af=1
.model sw1 sw vt=2.5 vh=0.1 ron=50 roff=1e6
.noise v(8) vin dec 10 10 1g 1
.end